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| HT24LC08 CMOS 8K 2-Wire Serial EEPROM Features * Operating voltage: 2.2V~5.5V * Low power consumption - Operation: 5mA max. - Standby: 5mA max. * Internal organization: 10248 * 2-wire Serial Interface * Write cycle time: 5ms max. * Automatic erase-before-write operation * Partial page write allowed * 16-byte Page Write Mode * Write operation with built-in timer * Hardware controlled write protection * 40-year data retention * 106 rewrite cycles per word * Commerical temperature range (0C to +70C) * 8-pin DIP/SOP package General Description The HT24LC08 is an 8K-bit serial read/write non-volatile memory device using the CMOS floating gate process. Its 8192 bits of memory are organized into 1024 words and each word is 8 bits. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. Up to two HT24LC08 devices may be connected to the same 2-wire bus. The HT24LC08 is guaranteed for 1M erase/write cycles and 40-year data retention. Block Diagram Pin Assignment A0 1 8 2 7 3 6 4 5 VCC WP SCL SDA SCL SDA I/O C o n tro l L o g ic X D M e m o ry C o n tro l L o g ic E C HV Pum p A1 A2 VSS EEPROM A rra y WP HT24LC08 8 D IP -A /S O P -A P a g e B u ffe r YDEC A0~A2 VCC VSS A d d re s s C o u n te r S ense A M P R /W C o n tro l Pin Description Pin Name A0~A2 SDA SCL WP VSS VCC I/O I I/O I I 3/4 3/4 Address input Serial data Serial clock input Write protect Negative power supply, ground Positive power supply Description Rev. 1.20 1 November 4, 2002 HT24LC08 Absolute Maximum Ratings Operating Temperature (Commercial) ........................................................................................................ 0C to 70C Storage Temperature ............................................................................................................................ -50C to 125C Applied VCC Voltage with Respect to VSS ............................................................................................... -0.3V to 6.0V Applied Voltage on any Pin with Respect to VSS ........................................................................................................ -0.3V to VCC+0.3V Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol VCC ICC1 ICC2 VIL VIH VOL ILI ILO ISTB1 ISTB2 CIN COUT Parameter Operating Voltage Operating Current Operating Current Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Current Standby Current Input Capacitance (See Note) Output Capacitance (See Note) Test Conditions VCC 3/4 5V 5V 3/4 3/4 2.4V 5V 5V 5V 2.4V 3/4 3/4 Conditions 3/4 Read at 100kHz Write at 100kHz 3/4 3/4 IOL=2.1mA VIN=0 or VCC VOUT=0 or VCC VIN=0 or VCC VIN=0 or VCC f=1MHz 25C f=1MHz 25C Min. 2.2 3/4 3/4 -1 0.7VCC 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Ta=0C to 70C Max. 5.5 2 5 0.3VCC VCC+0.5 0.4 1 1 5 4 6 8 Unit V mA mA V V V mA mA mA mA pF pF Note: These parameters are periodically sampled but not 100% tested A.C. Characteristics Symbol fSK tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Note Note After this period the first clock pulse is generated Only relevant for repeated START condition 3/4 3/4 3/4 Remark 3/4 3/4 3/4 Standard Mode* Min. 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 Ta=0C to 70C VCC=5V10% Min. 3/4 600 1200 3/4 3/4 600 600 0 100 600 Max. 400 3/4 3/4 300 300 3/4 3/4 3/4 3/4 3/4 kHz ns ns ns ns ns ns ns ns ns Unit Rev. 1.20 2 November 4, 2002 HT24LC08 Symbol tAA tBUF Parameter Output Valid from Clock Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time Remark 3/4 Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 Standard Mode* Min. 3/4 4700 Max. 3500 3/4 VCC=5V10% Min. 3/4 1200 Max. 900 3/4 ns ns Unit tSP tWR 3/4 3/4 100 5 3/4 3/4 50 5 ns ms Notes: These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.2V to 5.5V For relative timing, refer to timing diagrams Functional Description * Serial clock (SCL) * Start condition The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. * Serial data (SDA) A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). * Stop condition The SDA pin is bidirectional for serial data transfer. The pin is open drain driven and may be wired-OR with any number of other open drain or open collector devices. * A0, A1, A2 A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). * Acknowledge The HT24LC08 uses the A2 input for hard wire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins have no connection. * Write protect (WP) All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. D a ta a llo w e d to c h a n g e SDA The HT24LC08 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when the connection is grounded. When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status At VCC At VSS Protect Array Full Array (8K) Normal Read/Write Operations SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid S to p c o n d itio n Device addressing The 8K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. The 8K EEPROM uses the A2 device address bit with the next two bits for memory page addressing. The A2 bit must compare its corresponding hard-wired input pin. The A1 and A0 pins have no connection. These page addressing bits on the 8K device should be considered the most significant bits of the data word ad3 November 4, 2002 Memory organization Internally organized with 1024 8-bit words, the 8K requires a 10-bit data word address for random word addressing. Device operations * Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition. Rev. 1.20 HT24LC08 dress which follows. The A0, A1 and A2 pins have no connection. The 8th bit device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. 1 0 1 0 A2 A1 A0 R /W cremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. * Acknowledge polling D e v ic e A d d r e s s Write operations * Byte write A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until write is complete (refer to Byte write timing). * Page write Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W=0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is completed, then the device will return the ACK and the master can then proceed with the next read or write command. S e n d W r ite C o m m a n d S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o n tro l B y te w ith R /W = 0 The 8K EEPROM is capable of a 16-byte page write. A page write is initiated in the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to 15 more data words. The EEPROM will respond with a z e ro a f t e r e a c h d a t a w o r d r e c e i v e d . T h e microcontroller must terminate the page write sequence with a stop condition (refer to Page write timing). The data word address lower four bits are internally inD e v ic e a d d r e s s SDA S S ta rt A2 A1 A0 R /W ACK ACK W o rd a d d re s s (A C K = 0 )? Yes N e x t O p e r a tio n No Acknowledge polling flow DATA P ACK S to p Byte write timing D e v ic e a d d r e s s SDA S S ta rt ACK ACK ACK W o rd a d d re s s DATA n DATA n+1 DATA n+x P ACK S to p Page write timing Rev. 1.20 4 November 4, 2002 HT24LC08 * Write protect * Random read The HT24LC08 can be used as a serial ROM when the WP pin is connected to VCC . Programming will be in h ib i t ed and t he ent i r e m em or y w i l l b e write-protected. * Read operations Read operations are initiated in the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. * Current address read A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Random read timing). * Sequential read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Current read timing). D e v ic e a d d r e s s SDA S S ta rt A2 A1 A0 ACK Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition. DATA S to p P NoACK Current read timing D e v ic e a d d r e s s SDA S S ta rt A2 A1 A0 W o rd a d d re s s S D e v ic e a d d r e s s DATA S to p P NoACK ACK ACK S ta rt ACK Random read timing D e v ic e a d d r e s s SDA S S ta rt ACK ACK DATA n DATA n+1 DATA n+x P ACK S to p Sequential read timing Rev. 1.20 5 November 4, 2002 HT24LC08 Timing Diagrams t. SCL tS SDA SDA OUT U :S T A tR tL tH OW D :S T A tH IG H tH D :D A T tS U :D A T tS tB U :S T O tS P tA A U. V a lid V a lid SCL SDA 8 th b it W o rd n S to p c o n d itio n ACK tW R S to p c o n d itio n Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. Rev. 1.20 6 November 4, 2002 HT24LC08 Package Information 8-pin DIP (300mil) outline dimensions A B 1 8 5 4 H C D E . G = I Symbol A B C D E F G H I a Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375 15 Rev. 1.20 7 November 4, 2002 HT24LC08 8-pin SOP (150mil) outline dimensions A 1 8 5 B 4 C C' G D E . H = Symbol A B C C D E F G H a Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10 Rev. 1.20 8 November 4, 2002 HT24LC08 Product Tape and Reel Specifications Reel dimensions T2 D A B C T1 SOP 8N Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.15 12.8+0.3 -0.2 18.20.2 Rev. 1.20 9 November 4, 2002 HT24LC08 Carrier tape dimensions D E . P0 P1 t W C B0 D1 P K0 A0 SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3 Rev. 1.20 10 November 4, 2002 HT24LC08 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 11 November 4, 2002 |
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